In a NAND-type flash memory, when data is written and erased in the memory cells, a voltage higher than a power-supply voltage is applied to the control gate line in a selected block of memory cells. To supply this higher voltage, a voltage switching circuit that switches the power-supply voltage to a higher voltage is connected to a row decoder circuit. Such a voltage switching circuit generally includes plural kinds of high withstand voltage enhancement-type or depletion-type MOS transistors or the like.
Voltages of, for example, about 15 V to 40 V, are applied to gates of these transistors when data is being written in a memory cell block. At these voltages, there is a possibility that, over time, the threshold voltages of the transistors will degrade or the current driving capability will be reduced as a result of voltage stress on the gate electrodes and gate insulator, and an increased variation in circuit operation speed, or an increased delay in operation execution time, occurs. One approach to reducing the voltage stress is to increase the thickness of the gate insulation film. As a result, the resistance to voltage stress is enhanced, but the current driving capability of the resulting transistor is decreased.